篇一：5-单片机+外文文献+英文文献+外文翻译中英对照
AT89C51的介绍
（原文出处：http：//yang63.go.nease.net/resource/mcu.htm）
描述
AT89C51是一个低电压，高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。和128字节的存取数据存储器（RAM），这种器件采用ATMEL公司的高密度、不容易丢失存储技术生产，并且能够与MCS-51系列的单片机兼容。片内含有8位中央处理器和闪烁存储单元，有较强的功能的AT89C51单片机能够被应用到控制领域中。
功能特性
AT89C51提供以下的功能标准：4K字节闪烁存储器，128字节随机存取数据存储器，32个I/O口，2个16位定时/计数器，1个5向量两级中断结构，1个串行通信口，片内震荡器和时钟电路。另外，AT89C51还可以进行0HZ的静态逻辑操作，并支持两种软件的节电模式。闲散方式停止中央处理器的工作，能够允许随机存取数据存储器、定时/计数器、串行通信口及中断系统继续工作。掉电方式保存随机存取数据存储器中的内容，但震荡器停止工作并禁止其它所有部件的工作直到下一个复位。
引脚描述
VCC：电源电压 GND：地 P0口：
P0口是一组8位漏极开路双向I/O口，即地址/数据总线复用口。作为输出口时，每一个管脚都能够驱动8个TTL电路。当“1”被写入P0口时，每个管脚都能够作为高阻抗输入端。P0口还能够在访问外部数据存储器或程序存储器时，转换地址和数据总线复用，并在这时激活内部的上拉电阻。P0口在闪烁编程时，P0口接收指令，在程序校验时，输出指令，需要接电阻。
沈阳航空工业学院电子工程系毕业设计（外文翻译）
P1口：
P1口一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动4个TTL电路。对端口写“1”，通过内部的电阻把端口拉到高电平，此时可作为输入口。因为内部有电阻，某个引脚被外部信号拉低时输出一个电流。闪烁编程时和程序校验时，P1口接收低8位地址。
P2口：
P2口是一个内部带有上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动4个TTL电路。对端口写“1”，通过内部的电阻把端口拉到高电平，此时，可作为输入口。因为内部有电阻，某个引脚被外部信号拉低时会输出一个电流。在访问外部程序存储器或16位地址的外部数据存储器时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器时，P2口线上的内容在整个运行期间不变。闪烁编程或校验时，P2口接收高位地址和其它控制信号。
P3口：
P3口是一组带有内部电阻的8位双向I/O口，P3口输出缓冲故可驱动4个TTL电路。对P3口写如“1”时，它们被内部电阻拉到高电平并可作为输入端时，被外部拉低的P3口将用电阻输出电流。
P3口除了作为一般的I/O口外，更重要的用途是它的第二功能，如下表所示：
P3- 2 -
RST：
复位输入。当震荡器工作时，RET引脚出现两个机器周期以上的高电平将使单片机复位。
ALE/PROG：
当访问外部程序存储器或数据存储器时，ALE输出脉冲用于锁存地址的低8位字节。即使不访问外部存储器，ALE以时钟震荡频率的1/16输出固定的正脉冲信号，因此它可对输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲时，闪烁存储器编程时，这个引脚还用于输入编程脉冲。如果必要，可对特殊寄存器区中的8EH单元的D0位置禁止ALE操作。这个位置后只有一条MOVX和MOVC指令ALE才会被应用。此外，这个引脚会微弱拉高，单片机执行外部程序时，应设置ALE无效。
：
程序储存允许输出是外部程序存储器的读选通信号，当AT89C51由外部程序存储器读取指令时，每个机器周期两次PSEN 有效，即输出两个脉冲。在此期间，当访问外部数据存储器时，这两次有效的PSEN 信号不出现。
EA/VPP：
外部访问允许。欲使中央处理器仅访问外部程序存储器，EA端必须保持低电平。需要注意的是：如果加密位LBI被编程，复位时内部会锁存EA端状态。如EA端为高电平，CPU则执行内部程序存储器中的指令。闪烁存储器编程时，该引脚加上+12V的编程允许电压VPP，当然这必须是该器件是使用12V编程电压VPP。
XTAL1：震荡器反相放大器及内部时钟发生器的输入端。 XTAL2：震荡器反相放大器的输出端。
时钟震荡器
AT89C51中有一个用于构成内部震荡器的高增益反相放大器，引脚XTAL1和XTAL2分别是该放大器的输入端和输出端。这个放大器与作为反馈元件的片外石英晶体或陶瓷谐振器一起构成自然震荡器。 外接石英晶体及电容C1，C2接在放大器的反馈回路中构成并联震荡电路。对外接电容C1，C2虽然没有十分严格的要求，但
沈阳航空工业学院电子工程系毕业设计（外文翻译）
电容容量的大小会轻微影响震荡频率的高低、震荡器工作的稳定性、起振的难易程序及温度稳定性。如果使用石英晶体，我们推荐电容使用30PF±10PF，而如果使用陶瓷振荡器建议选择40PF±10PF。用户也可以采用外部时钟。采用外部时钟的电路如图示。这种情况下，外部时钟脉冲接到XTAL1端，即内部时钟发生器的输入端，XTAL2则悬空。由于外部时钟信号是通过一个2分频触发器后作为内部时钟信号的，所以对外部时钟信号的占空比没有特殊要求，但最小高电平持续时间和最大的低电平持续时间应符合产品技术条件的要求。
内部振荡电路 外部振荡电路
闲散节电模式
AT89C51有两种可用软件编程的省电模式，它们是闲散模式和掉电工作模式。这两种方式是控制专用寄存器PCON中的PD和IDL位来实现的。PD是掉电模式，当PD=1时，激活掉电工作模式，单片机进入掉电工作状态。IDL是闲散等待方式，当IDL=1，激活闲散工作状态，单片机进入睡眠状态。如需要同时进入两种工作模式，即PD和IDL同时为1，则先激活掉电模式。在闲散工作模式状态，中央处理器CPU保持睡眠状态，而所有片内的外设仍保持激活状态，这种方式由软件产生。此时，片内随机存取数据存储器和所有特殊功能寄存器的内容保持不变。闲散模式可由任何允许的中断请求或硬件复位终止。终止闲散工作模式的方法有两种，一是任何一条被允许中断的事件被激活，IDL被硬件清除，即刻终止闲散工作模式。程序会首先影响中断，进入中断服务程序，执行完中断服务程序，并紧随RETI指令后，下一条要执行
- 4 -
的指令就是使单片机进入闲散工作模式，那条指令后面的一条指令。二是通过硬件复位也可将闲散工作模式终止。需要注意的是：当由硬件复位来终止闲散工作模式时，中央处理器CPU通常是从激活空闲模式那条指令的下一条开始继续执行程序的，要完成内部复位操作，硬件复位脉冲要保持两个机器周期有效，在这种情况下，内部禁止中央处理器CPU访问片内RAM，而允许访问其他端口，为了避免可能对端口产生的意外写入：激活闲散模式的那条指令后面的一条指令不应是一条对端口或外部存储器的写入指令。
掉电模式
在掉电模式下，振荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM和特殊功能寄存器的内容在中指掉电模式前被冻结。退出掉电模式的唯一方法是硬件复位，复位后将从新定义全部特殊功能寄存器但不改变RAM中的内容，在VCC恢复到正常工作电平前，复位应无效切必须保持一定时间以使振荡器从新启动并稳定工作。
闲散和掉电模式外部引脚状态。
程序存储器的加密
AT89C51可使用对芯片上的三个加密位LB1，LB2，LB3进行编程（P）或不编程（U）得到如下表所示的功能：
篇二：单片机毕业参考英文文献及翻译
附录：英文技术资料翻译
英文原文：
Structure and function of the MCS-51 series
Structure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers .
An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. ( 4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. ( 6) Five cut off cutting off the control system of the source . ( 7) One all duplexing serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. ( 8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertas now at most. Every the above-mentioned part was joined through the inside data bus .Among
them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.
There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to
arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.
8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing
Output grade , P3 of mouth , P1 of P1 , connect with inside have load resistance of drawing , every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way . Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outerly . Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first . As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base , in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially , make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally,as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective , should sustain 24 shake cycle (namely 2 machine cycles ) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal:
Restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST ) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal insidly. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake,
can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running,should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with the oscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.
注：文献来源
http://wenku.baidu.com/view/30ac732a4b73f242336c5fd6.html
篇三：单片机基础外文翻译参考文献
单片机基础外文翻译参考文献
(文档含中英文对照即英文原文和中文翻译)
原文:
Fundamentals of Single-chip Microcomputer
Dr. Dobbs MacintoshJournal
Abstract
The single-chip microcomputer is the culmination of both the development of the digital computer and the integrated circuit arguably the tow most significant inventions of the 20th century .
These tow types of architecture are found in single-chip
microcomputer. Some employ the split program/data memory of the Harvard architecture, shown in Fig.3-5A-1, others follow the philosophy, widely adapted for general-purpose computers and microprocessors, of making no logical distinction between program and data memory as in the Princeton architecture.
In general terms a single-chip microcomputer is characterized by the incorporation of all the units of a computer into a single device.
Keyword: Single-chip Microcomputer ROM RAM Programming Algorithm
Features
? Compatible with MCS-51? Products
? 4K Bytes of In-System Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
? Fully Static Operation: 0 Hz to 24 MHz
? Three-level Program Memory Lock
? 128 x 8-bit Internal RAM
? 32 Programmable I/O Lines
? Two 16-bit Timer/Counters
? Six Interrupt Sources
? Programmable Serial Channel
? Low-power Idle and Power-down Modes
Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and
iscompatible with the industry-standard MCS-51 instruction set and pinout. The
on-chipFlash allows the program memory to be reprogrammed in-system or by a
conventionalnonvolatile memory programmer. By combining a versatile 8-bit CPU with Flashon a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which providesa highly-flexible and cost-effective solution to many embedded control
applications.The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level
interrupt architecture,a full duplex serial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Modestops the CPU while allowing the RAM, timer/counters,serial port and interrupt system to continue functioning. ThePower-down Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the nexthardware reset.
Pin Configurations
Block Diagram
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs.
Port 0 may also be configured to be the multiplexed loworderaddress/data bus
during accesses to external programand data memory. In this mode P0 has
internalpullups.
Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during program verification.
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal
pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are
pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal
pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order
《单片机英文参考文献》出自：百味书屋
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